In general, a semiconductor memory device accesses data in synchronization with a clock signal provided from a circuit that is located outside the memory device. A Double Data Rate (DDR) semiconductor memory device receives data in synchronization with the rising and falling edges of a clock signal inputted from a circuit or a memory controller located outside the DDR memory device. In a DDR semiconductor memory device, serial data received through a data pad are inputted as parallel data so as to store the aligned data in the memory cells by the unit of two bits. Furthermore, a Double Data Rate 2 (DDR2) semiconductor memory device utilizes a clock speed with twice the frequency of a clock signal used in a DDR semiconductor memory device in receiving data. In a DDR2 semiconductor memory device, serial data received through a data pad are inputted as parallel data so as to store the aligned data in the memory cells by the unit of four bits.
A combo semiconductor memory device is designed to support the DDR or DDR2 mode, and one of the two modes is selected through a metal option process during a manufacturing process. That is, in a combo semiconductor memory device, the number of bits of the data aligned in parallel is controlled using a metal option. And the speed of inputting or outputting a data in the DDR2 mode is twice as fast as that in the DDR mode.
The metal option refers to an option for sputtering a specific portion of a metal line used as an interconnection such that the specific portion operates like a switch. When such a metal option is used to control the bit number of data aligned in parallel, a mask used in the DDR mode and a mask used in the DDR2 mode should be manufactured separately.